Testing for Coupled Cells in Random-Access Memories

J. Savir, W. H. McAnney, S. R. Vecchio

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

Two test strategies for memory testing are compared for their ability to detect coupled-cell faults in an n word by 1 bit random access memory. In both strategies the data-in line is randomly driven. One of the two strategies uses random selection of both the address lines and the read/write control. The other strategy sequentially cycles through the address space with deterministic setting of the read/write control. The relative merit of the two strategies is measured by the average number of accesses per address needed to meet a standard test quality level.

Original languageEnglish (US)
Pages (from-to)1177-1180
Number of pages4
JournalIEEE Transactions on Computers
Volume40
Issue number10
DOIs
StatePublished - Oct 1991
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

Keywords

  • Escape probability
  • memory testing
  • pattern-sensitive fault
  • random testing
  • signal probability

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