Abstract
Two test strategies for memory testing are compared for their ability to detect coupled-cell faults in an n word by 1 bit random access memory. In both strategies the data-in line is randomly driven. One of the two strategies uses random selection of both the address lines and the read/write control. The other strategy sequentially cycles through the address space with deterministic setting of the read/write control. The relative merit of the two strategies is measured by the average number of accesses per address needed to meet a standard test quality level.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1177-1180 |
| Number of pages | 4 |
| Journal | IEEE Transactions on Computers |
| Volume | 40 |
| Issue number | 10 |
| DOIs | |
| State | Published - Oct 1991 |
| Externally published | Yes |
All Science Journal Classification (ASJC) codes
- Software
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics
Keywords
- Escape probability
- memory testing
- pattern-sensitive fault
- random testing
- signal probability