Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection

Jacob Savir

doi:10.1109/TC.1980.1675595

Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection

Jacob Savir

Research output: Contribution to journal › Article › peer-review

15 Scopus citations

Abstract

Intermittent faults in combinational circuits may appear and disappear randomly; hence, their detection requires many repeated applications of test vectors. Since testing reduces the time available for computation, it is necessary to efficiently minimize the time required for a test, while still achieving a high degree of fault detection. This paper presents an optimal random test procedure to detect intermittent failures. The algorithm maximizes the probability of fault detection byoptimally choosing the input vector probabilities.

Original language	English (US)
Pages (from-to)	410-416
Number of pages	7
Journal	IEEE Transactions on Computers
Volume	C-29
Issue number	5
DOIs	https://doi.org/10.1109/TC.1980.1675595
State	Published - May 1980
Externally published	Yes

All Science Journal Classification (ASJC) codes

Software
Theoretical Computer Science
Hardware and Architecture
Computational Theory and Mathematics

Keywords

Error latency
intermittent fault detection
irredundant circuit
maximum likelihood estimator
random testing

Access to Document

10.1109/TC.1980.1675595

Cite this

@article{427d0661ed1f4492af0734e5d270171d,

title = "Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection",

abstract = "Intermittent faults in combinational circuits may appear and disappear randomly; hence, their detection requires many repeated applications of test vectors. Since testing reduces the time available for computation, it is necessary to efficiently minimize the time required for a test, while still achieving a high degree of fault detection. This paper presents an optimal random test procedure to detect intermittent failures. The algorithm maximizes the probability of fault detection byoptimally choosing the input vector probabilities.",

keywords = "Error latency, intermittent fault detection, irredundant circuit, maximum likelihood estimator, random testing",

author = "Jacob Savir",

year = "1980",

month = may,

doi = "10.1109/TC.1980.1675595",

language = "English (US)",

volume = "C-29",

pages = "410--416",

journal = "IEEE Transactions on Computers",

issn = "0018-9340",

publisher = "IEEE Computer Society",

number = "5",

}

TY - JOUR

T1 - Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection

AU - Savir, Jacob

PY - 1980/5

Y1 - 1980/5

N2 - Intermittent faults in combinational circuits may appear and disappear randomly; hence, their detection requires many repeated applications of test vectors. Since testing reduces the time available for computation, it is necessary to efficiently minimize the time required for a test, while still achieving a high degree of fault detection. This paper presents an optimal random test procedure to detect intermittent failures. The algorithm maximizes the probability of fault detection byoptimally choosing the input vector probabilities.

AB - Intermittent faults in combinational circuits may appear and disappear randomly; hence, their detection requires many repeated applications of test vectors. Since testing reduces the time available for computation, it is necessary to efficiently minimize the time required for a test, while still achieving a high degree of fault detection. This paper presents an optimal random test procedure to detect intermittent failures. The algorithm maximizes the probability of fault detection byoptimally choosing the input vector probabilities.

KW - Error latency

KW - intermittent fault detection

KW - irredundant circuit

KW - maximum likelihood estimator

KW - random testing

UR - https://www.scopus.com/pages/publications/0019020807

UR - https://www.scopus.com/pages/publications/0019020807#tab=citedBy

U2 - 10.1109/TC.1980.1675595

DO - 10.1109/TC.1980.1675595

M3 - Article

AN - SCOPUS:0019020807

SN - 0018-9340

VL - C-29

SP - 410

EP - 416

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

IS - 5

ER -

Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection

Abstract

All Science Journal Classification (ASJC) codes

Keywords

Access to Document

Other files and links

Fingerprint

Cite this