The Relatively Simple CPU Simulator is an instructional aid for students studying computer architecture and CPU design, typically at the junior or senior level. It simulates the Relatively Simple CPU, a 16-instruction processor introduced in the textbook Computer Systems Organization and Architecture. Students first enter an assembly language program, which is assembled by the simulator. After correcting any syntax errors, the user simulates the fetch, decode, and execute cycles for each instruction in the program. The user may simulate the execution of the program by clock cycle, by instruction, using breakpoints, or as a single, continuous execution. The simulator uses animation to give students a more intuitive understanding of how the CPU fetches, decodes, and executes instructions. It shows the flow of data within the CPU's register section. A pop-up window animates data flow within the ALU whenever it is active. The control unit highlights signals asserted by the control unit and used in the rest of the CPU. Users may select either a hard-wired or microcoded control unit. The Relatively Simple CPU simulator is coded as a platform-independent Java applet that can be executed within any Java-enabled web browser. The simulator and its source code are freely available under the GNU Public License.
|Number of pages
|ASEE Annual Conference Proceedings
|Published - Dec 1 2001
|2001 ASEE Annual Conference and Exposition: Peppers, Papers, Pueblos and Professors - Albuquerque, NM, United States
Duration: Jun 24 2001 → Jun 27 2001
All Science Journal Classification (ASJC) codes
- General Engineering