Wallace Trees are combinatorial logic circuits used to multiply binary integers. Constructed using carry-save adders, they are a fast, efficient method to implement multiplication. Since these adders do not propagate carry values between bits, they are faster than parallel adders and can produce multiplication products faster than other multiplication hardware. This paper presents the Wallace Tree Simulator, an instructional aid for students studying computer architecture and CPU design, typically at the junior or senior level. It simulates 4-, 6-, and 8-bit Wallace Tree multipliers, as presented in the textbook Computer Systems Organization and Architecture. Students select the size of the Wallace Tree to be simulated and enter values for the operands to be multiplied. The simulator shows the partial products generated by the Wallace Tree, and the results generated by each carry-save adder in the tree, as well as the final product. Students can also examine the internal organization of the carry-save adders to see how they generate their results within the tree. The Wallace Tree Simulator is coded as a platform-independent Java applet that can be executed within any Java-enabled web browser. The simulator and its source code are freely available under the terms of the GNU Public License.
|Original language||English (US)|
|Number of pages||7|
|Journal||ASEE Annual Conference Proceedings|
|State||Published - Dec 1 2003|
|Event||2003 ASEE Annual Conference and Exposition: Staying in Tune with Engineering Education - Nashville, TN, United States|
Duration: Jun 22 2003 → Jun 25 2003
All Science Journal Classification (ASJC) codes