Thermal considerations for monolithic integration of three-dimensional integrated circuits

A. K. Henning; B. Rajendran; B. Cronquist; Z. Or-Bach

doi:10.1109/S3S.2013.6716559

Thermal considerations for monolithic integration of three-dimensional integrated circuits

A. K. Henning, B. Rajendran, B. Cronquist, Z. Or-Bach

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

A major consideration for practical integration of 3D integrated circuits is compatibility of the thermal processes used to build new transistors in the vertical dimension, with sustained viability of the devices already fabricated beneath. Major contributions to the thermal profile of IC processes are laser-based anneals, rapid-thermal anneals and deposition processes, and traditional furnace processes for both annealing and film deposition. In this work, we consider the thermal compatibility of laser annealing of newly built 3D structures, with the ICs lying beneath.

Original language	English (US)
Title of host publication	2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013
Publisher	IEEE Computer Society
ISBN (Print)	9781479913602
DOIs	https://doi.org/10.1109/S3S.2013.6716559
State	Published - 2013
Externally published	Yes
Event	2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013 - Monterey, CA, United States Duration: Oct 7 2013 → Oct 10 2013

Publication series

Name	2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013

Other

Other	2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013
Country/Territory	United States
City	Monterey, CA
Period	10/7/13 → 10/10/13

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/S3S.2013.6716559

Cite this

Henning, A. K., Rajendran, B., Cronquist, B., & Or-Bach, Z. (2013). Thermal considerations for monolithic integration of three-dimensional integrated circuits. In 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013 Article 6716559 (2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013). IEEE Computer Society. https://doi.org/10.1109/S3S.2013.6716559

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title = "Thermal considerations for monolithic integration of three-dimensional integrated circuits",

abstract = "A major consideration for practical integration of 3D integrated circuits is compatibility of the thermal processes used to build new transistors in the vertical dimension, with sustained viability of the devices already fabricated beneath. Major contributions to the thermal profile of IC processes are laser-based anneals, rapid-thermal anneals and deposition processes, and traditional furnace processes for both annealing and film deposition. In this work, we consider the thermal compatibility of laser annealing of newly built 3D structures, with the ICs lying beneath.",

author = "Henning, {A. K.} and B. Rajendran and B. Cronquist and Z. Or-Bach",

year = "2013",

doi = "10.1109/S3S.2013.6716559",

language = "English (US)",

isbn = "9781479913602",

series = "2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013",

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booktitle = "2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013",

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note = "2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013 ; Conference date: 07-10-2013 Through 10-10-2013",

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Henning, AK, Rajendran, B, Cronquist, B & Or-Bach, Z 2013, Thermal considerations for monolithic integration of three-dimensional integrated circuits. in 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013., 6716559, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013, IEEE Computer Society, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013, Monterey, CA, United States, 10/7/13. https://doi.org/10.1109/S3S.2013.6716559

Thermal considerations for monolithic integration of three-dimensional integrated circuits. / Henning, A. K.; Rajendran, B.; Cronquist, B. et al.
2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013. IEEE Computer Society, 2013. 6716559 (2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Henning, A. K.

AU - Rajendran, B.

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AB - A major consideration for practical integration of 3D integrated circuits is compatibility of the thermal processes used to build new transistors in the vertical dimension, with sustained viability of the devices already fabricated beneath. Major contributions to the thermal profile of IC processes are laser-based anneals, rapid-thermal anneals and deposition processes, and traditional furnace processes for both annealing and film deposition. In this work, we consider the thermal compatibility of laser annealing of newly built 3D structures, with the ICs lying beneath.

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M3 - Conference contribution

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BT - 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013

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Henning AK, Rajendran B, Cronquist B, Or-Bach Z. Thermal considerations for monolithic integration of three-dimensional integrated circuits. In 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013. IEEE Computer Society. 2013. 6716559. (2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013). doi: 10.1109/S3S.2013.6716559

Thermal considerations for monolithic integration of three-dimensional integrated circuits

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