Skip to main navigation Skip to search Skip to main content

TrackGNN: A Highly Parallelized and Self-Adaptive GNN Accelerator for Track Reconstruction on FPGAs

  • Shuyang Li
  • , Hanqing Zhang
  • , Ruiqi Chen
  • , Bruno Da Silva
  • , Giorgian Borca-Tasciuc
  • , Dantong Yu
  • , Cong Callie Hao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Track reconstruction is essential in high-energy physics (HEP) to identify charged particles and understand their properties. Graph neural networks (GNNs) show great promise as an alternative. However, the stringent real-time and low-latency requirements in trigger decision pose significant challenges for deploying GNN inference in modern particle tracking systems. In this work, we achieve real-time track reconstruction on FPGAs by proposing TrackGNN, a high-performance FPGA-based dataflow accelerator. TrackGNN leverages a streaming architecture with multiple levels of parallelism. In particular, we introduce a novel self-adaptive renaming mechanism to improve data locality in the graph structure, reducing initiation delays and pipeline stalls. We also explore a fixed-point quantization strategy to improve energy efficiency and maintain model accuracy. Experimental results show that TrackGNN achieves 27.6 × and 4.9 - 101.1 × speedup over CPUs and GPUs, respectively, along with 55.36 × and 515.46 × better energy efficiency. Compared to the state-of-the-art FPGA-based GNN accelerator, TrackGNN delivers a 16.67% performance boost with FlowGNN [1],a gain directly attributable to the proposed renaming process, and 5.7 × speedup over overlay architectures. TrackGNN is fully open-sourced and available at https://github.com/silvenachen/TrackGNN.

Original languageEnglish (US)
Title of host publicationProceedings of the 27th International Symposium on Quality Electronic Design, ISQED 2026
PublisherIEEE Computer Society
ISBN (Electronic)9798331583613
DOIs
StatePublished - 2026
Event27th International Symposium on Quality Electronic Design, ISQED 2026 - San Francisco, United States
Duration: Apr 8 2026 → Apr 10 2026

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Conference

Conference27th International Symposium on Quality Electronic Design, ISQED 2026
Country/TerritoryUnited States
CitySan Francisco
Period4/8/26 → 4/10/26

All Science Journal Classification (ASJC) codes

  • Safety, Risk, Reliability and Quality
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Keywords

  • Dataflow Architecture
  • Graph Neural Network (GNN)
  • High Energy Physics
  • Track Reconstruction

Fingerprint

Dive into the research topics of 'TrackGNN: A Highly Parallelized and Self-Adaptive GNN Accelerator for Track Reconstruction on FPGAs'. Together they form a unique fingerprint.

Cite this