Abstract
Protecting the on-chip cache memories against soft errors has become an increasing challenge in designing new generation reliable microprocessors. Previous efforts have mainly focused on improving the reliability of the cache data arrays. Due to its crucial importance to the correctness of cache accesses, the tag array demands high reliability against soft errors while the data array is fully protected. Exploiting the address locality of memory accesses, we propose to duplicate most recently accessed tag entries in a small Tag Replication Buffer (TRB) thus to protect the information integrity of the tag array In the data cache with low performance, energy and area overheads. A Selective-TRB scheme is further proposed to protect only tag entries of dirty cachelines. The experimental results show that the Selective-TRB scheme achieves a higher access-with-repllca (AWR) rate of 97.4% for the dirty-cacheline tags. To provide a comprehensive evaluation of the tag-array reliability, we also conduct an architectural vulnerability factor (AVF) analysis for the tag array and propose a refined metric, detected-withoutrepllca-AVF (DOR-AVF), which combines the AVF and AWR analysis. Based on our DOR-AVF analysis, a TRB scheme with early write-back (EWB) is proposed, which achieves a zero DORAVF at a negligible performance overhead.
Original language | English (US) |
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Title of host publication | Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010 |
Pages | 310-315 |
Number of pages | 6 |
DOIs | |
State | Published - Oct 20 2010 |
Event | IEEE Annual Symposium on VLSI, ISVLSI 2010 - Lixouri, Kefalonia, Greece Duration: Jul 5 2010 → Jul 7 2010 |
Other
Other | IEEE Annual Symposium on VLSI, ISVLSI 2010 |
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Country/Territory | Greece |
City | Lixouri, Kefalonia |
Period | 7/5/10 → 7/7/10 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering