Abstract
In this paper, we propose and implement a vector processing system that includes two identical vector microprocessors embedded in two FPGA chips. Each vector microprocessor supports floating-point calculations and efficient sparse matrix operations. Dense matrix-matrix multiplication and sparse matrix-vector multiplication with benchmark matrices from various application domains were run on the system to evaluate its performance. The resulting calculation times are compared with those of a commercial PC to show the effectiveness of our approach.
Original language | English (US) |
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Title of host publication | Proceedings - IEEE Computer Society Annual Symposium on VLSI |
Subtitle of host publication | Emerging VLSI Technologies and Architectures |
Pages | 447-448 |
Number of pages | 2 |
DOIs | |
State | Published - Nov 28 2007 |
Event | IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07 - Porto Alegre, Brazil Duration: Mar 9 2007 → Mar 11 2007 |
Other
Other | IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07 |
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Country/Territory | Brazil |
City | Porto Alegre |
Period | 3/9/07 → 3/11/07 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering