Vector processing support for FPGA-oriented high performance applications

Yang Hongyan; Wang Shuai; Sotirios Ziavras; Hu Jie

doi:10.1109/ISVLSI.2007.100

Vector processing support for FPGA-oriented high performance applications

Yang Hongyan, Wang Shuai, Sotirios Ziavras, Hu Jie

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

In this paper, we propose and implement a vector processing system that includes two identical vector microprocessors embedded in two FPGA chips. Each vector microprocessor supports floating-point calculations and efficient sparse matrix operations. Dense matrix-matrix multiplication and sparse matrix-vector multiplication with benchmark matrices from various application domains were run on the system to evaluate its performance. The resulting calculation times are compared with those of a commercial PC to show the effectiveness of our approach.

Original language	English (US)
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publication	Emerging VLSI Technologies and Architectures
Pages	447-448
Number of pages	2
DOIs	https://doi.org/10.1109/ISVLSI.2007.100
State	Published - Nov 28 2007
Event	IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07 - Porto Alegre, Brazil Duration: Mar 9 2007 → Mar 11 2007

Other

Other	IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07
Country/Territory	Brazil
City	Porto Alegre
Period	3/9/07 → 3/11/07

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/ISVLSI.2007.100

Cite this

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title = "Vector processing support for FPGA-oriented high performance applications",

abstract = "In this paper, we propose and implement a vector processing system that includes two identical vector microprocessors embedded in two FPGA chips. Each vector microprocessor supports floating-point calculations and efficient sparse matrix operations. Dense matrix-matrix multiplication and sparse matrix-vector multiplication with benchmark matrices from various application domains were run on the system to evaluate its performance. The resulting calculation times are compared with those of a commercial PC to show the effectiveness of our approach.",

author = "Yang Hongyan and Wang Shuai and Sotirios Ziavras and Hu Jie",

year = "2007",

month = nov,

day = "28",

doi = "10.1109/ISVLSI.2007.100",

language = "English (US)",

isbn = "0769528961",

pages = "447--448",

booktitle = "Proceedings - IEEE Computer Society Annual Symposium on VLSI",

note = "IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07 ; Conference date: 09-03-2007 Through 11-03-2007",

}

Hongyan, Y, Shuai, W, Ziavras, S & Jie, H 2007, Vector processing support for FPGA-oriented high performance applications. in Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures., 4208955, pp. 447-448, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07, Porto Alegre, Brazil, 3/9/07. https://doi.org/10.1109/ISVLSI.2007.100

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AU - Shuai, Wang

AU - Ziavras, Sotirios

AU - Jie, Hu

PY - 2007/11/28

Y1 - 2007/11/28

N2 - In this paper, we propose and implement a vector processing system that includes two identical vector microprocessors embedded in two FPGA chips. Each vector microprocessor supports floating-point calculations and efficient sparse matrix operations. Dense matrix-matrix multiplication and sparse matrix-vector multiplication with benchmark matrices from various application domains were run on the system to evaluate its performance. The resulting calculation times are compared with those of a commercial PC to show the effectiveness of our approach.

AB - In this paper, we propose and implement a vector processing system that includes two identical vector microprocessors embedded in two FPGA chips. Each vector microprocessor supports floating-point calculations and efficient sparse matrix operations. Dense matrix-matrix multiplication and sparse matrix-vector multiplication with benchmark matrices from various application domains were run on the system to evaluate its performance. The resulting calculation times are compared with those of a commercial PC to show the effectiveness of our approach.

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U2 - 10.1109/ISVLSI.2007.100

DO - 10.1109/ISVLSI.2007.100

M3 - Conference contribution

AN - SCOPUS:36349022540

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SN - 9780769528960

SP - 447

EP - 448

BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI

T2 - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07

Y2 - 9 March 2007 through 11 March 2007

ER -

Vector processing support for FPGA-oriented high performance applications

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