TY - GEN
T1 - Vector processing support for FPGA-oriented high performance applications
AU - Hongyan, Yang
AU - Shuai, Wang
AU - Ziavras, Sotirios G.
AU - Jie, Hu
PY - 2007
Y1 - 2007
N2 - In this paper, we propose and implement a vector processing system that includes two identical vector microprocessors embedded in two FPGA chips. Each vector microprocessor supports floating-point calculations and efficient sparse matrix operations. Dense matrix-matrix multiplication and sparse matrix-vector multiplication with benchmark matrices from various application domains were run on the system to evaluate its performance. The resulting calculation times are compared with those of a commercial PC to show the effectiveness of our approach.
AB - In this paper, we propose and implement a vector processing system that includes two identical vector microprocessors embedded in two FPGA chips. Each vector microprocessor supports floating-point calculations and efficient sparse matrix operations. Dense matrix-matrix multiplication and sparse matrix-vector multiplication with benchmark matrices from various application domains were run on the system to evaluate its performance. The resulting calculation times are compared with those of a commercial PC to show the effectiveness of our approach.
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U2 - 10.1109/ISVLSI.2007.100
DO - 10.1109/ISVLSI.2007.100
M3 - Conference contribution
AN - SCOPUS:36349022540
SN - 0769528961
SN - 9780769528960
T3 - Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures
SP - 447
EP - 448
BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI
T2 - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07
Y2 - 9 March 2007 through 11 March 2007
ER -