Verilog-A compact model for a novel Cu/SiO2/W quantum memristor

S. R. Nandakumar, Bipin Rajendran

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we develop a Verilog-A model for a memristive device that has shown non-volatile state transitions via half-integer quantized conductance states at room temperature and an on-off ratio of ∼ 103. The model captures the geometrical evolution of a nano-filament and maps it to conductance levels in the equivalent electrical circuit, thereby accurately capturing the DC I-V and transient response of the device. The suitability of the model for circuit simulations is illustrated via a 4 χ 4 crossbar array programming simulation in HSPICE which captures the multilevel programmability of the device.

Original languageEnglish (US)
Title of host publication2016 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages169-172
Number of pages4
ISBN (Electronic)9781509008179
DOIs
StatePublished - Oct 20 2016
Event2016 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2016 - Nuremberg, Germany
Duration: Sep 6 2016Sep 8 2016

Other

Other2016 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2016
CountryGermany
CityNuremberg
Period9/6/169/8/16

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Modeling and Simulation

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