Verilog-A compact model for a novel Cu/SiO2/W quantum memristor

S. R. Nandakumar; Bipin Rajendran

doi:10.1109/SISPAD.2016.7605174

Verilog-A compact model for a novel Cu/SiO₂/W quantum memristor

S. R. Nandakumar, Bipin Rajendran

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

In this paper, we develop a Verilog-A model for a memristive device that has shown non-volatile state transitions via half-integer quantized conductance states at room temperature and an on-off ratio of ∼ 10³. The model captures the geometrical evolution of a nano-filament and maps it to conductance levels in the equivalent electrical circuit, thereby accurately capturing the DC I-V and transient response of the device. The suitability of the model for circuit simulations is illustrated via a 4 χ 4 crossbar array programming simulation in HSPICE which captures the multilevel programmability of the device.

Original language	English (US)
Title of host publication	2016 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	169-172
Number of pages	4
ISBN (Electronic)	9781509008179
DOIs	https://doi.org/10.1109/SISPAD.2016.7605174
State	Published - Oct 20 2016
Event	2016 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2016 - Nuremberg, Germany Duration: Sep 6 2016 → Sep 8 2016

Other

Other	2016 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2016
Country/Territory	Germany
City	Nuremberg
Period	9/6/16 → 9/8/16

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Computer Science Applications
Modeling and Simulation

Access to Document

10.1109/SISPAD.2016.7605174

Cite this

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title = "Verilog-A compact model for a novel Cu/SiO2/W quantum memristor",

abstract = "In this paper, we develop a Verilog-A model for a memristive device that has shown non-volatile state transitions via half-integer quantized conductance states at room temperature and an on-off ratio of ∼ 103. The model captures the geometrical evolution of a nano-filament and maps it to conductance levels in the equivalent electrical circuit, thereby accurately capturing the DC I-V and transient response of the device. The suitability of the model for circuit simulations is illustrated via a 4 χ 4 crossbar array programming simulation in HSPICE which captures the multilevel programmability of the device.",

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booktitle = "2016 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2016",

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note = "2016 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2016 ; Conference date: 06-09-2016 Through 08-09-2016",

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Nandakumar, SR & Rajendran, B 2016, Verilog-A compact model for a novel Cu/SiO₂/W quantum memristor. in 2016 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2016., 7605174, Institute of Electrical and Electronics Engineers Inc., pp. 169-172, 2016 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2016, Nuremberg, Germany, 9/6/16. https://doi.org/10.1109/SISPAD.2016.7605174

Verilog-A compact model for a novel Cu/SiO₂/W quantum memristor. / Nandakumar, S. R.; Rajendran, Bipin.
2016 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 169-172 7605174.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - In this paper, we develop a Verilog-A model for a memristive device that has shown non-volatile state transitions via half-integer quantized conductance states at room temperature and an on-off ratio of ∼ 103. The model captures the geometrical evolution of a nano-filament and maps it to conductance levels in the equivalent electrical circuit, thereby accurately capturing the DC I-V and transient response of the device. The suitability of the model for circuit simulations is illustrated via a 4 χ 4 crossbar array programming simulation in HSPICE which captures the multilevel programmability of the device.

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