TY - GEN
T1 - VLSI design of stability routing protocol for sensors in manets
AU - Mandava, Vishnu
AU - Gururaj, Kiran
AU - Zakrevski, Lev
AU - Misra, Durga
PY - 2003
Y1 - 2003
N2 - Mobile hosts and wireless networking hardware are becoming more widely available unlike before. The data transmission between the nodes becomes more critical while considering the sensors in an ad-hoc network due to the unpredictable and variable mobility patterns of the nodes. The signal strength criteria that has been proved to be efficient for communication without any data loss between the mobile nodes is considered. The stability routing protocol [1, 8] has been proposed for ad-hoc network and is based on the signal strength and location stability. This paper presents the architecture of the chip that can be used for communication between the Surface Acoustic Wave (SAW) sensors [2] in an ad-hoc network. The architecture of the chip is divided into four main blocks namely Update and Transmitter unit (UTx), Routing Table generation Unit (RTU), Packet Forwarding and updating Unit (PFU) and Receiver Unit (RU). All these blocks use a centralized memory unit to access the data and are linked to a bus arbitrator. The memory unit has four Lookup Tables (LUT); Position LUT, Stability LUT, Routing LUT, Emergency LUT. A VHDL model was developed and simulated using the IEEE standard packages.
AB - Mobile hosts and wireless networking hardware are becoming more widely available unlike before. The data transmission between the nodes becomes more critical while considering the sensors in an ad-hoc network due to the unpredictable and variable mobility patterns of the nodes. The signal strength criteria that has been proved to be efficient for communication without any data loss between the mobile nodes is considered. The stability routing protocol [1, 8] has been proposed for ad-hoc network and is based on the signal strength and location stability. This paper presents the architecture of the chip that can be used for communication between the Surface Acoustic Wave (SAW) sensors [2] in an ad-hoc network. The architecture of the chip is divided into four main blocks namely Update and Transmitter unit (UTx), Routing Table generation Unit (RTU), Packet Forwarding and updating Unit (PFU) and Receiver Unit (RU). All these blocks use a centralized memory unit to access the data and are linked to a bus arbitrator. The memory unit has four Lookup Tables (LUT); Position LUT, Stability LUT, Routing LUT, Emergency LUT. A VHDL model was developed and simulated using the IEEE standard packages.
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U2 - 10.1109/ITRE.2003.1270591
DO - 10.1109/ITRE.2003.1270591
M3 - Conference contribution
AN - SCOPUS:84893920436
SN - 0780377249
SN - 9780780377240
T3 - Proceedings, ITRE 2003 - International Conference on Information Technology: Research and Education
SP - 147
EP - 151
BT - Proceedings, ITRE 2003 - International Conference on Information Technology
T2 - 2003 International Conference on Information Technology: Research and Education, ITRE 2003
Y2 - 11 August 2003 through 13 August 2003
ER -