W-polycide dual-gate structure for sub- 1/4 micron low-voltage CMOS technology

J. Bevk; G. E. Georgiou; M. Frei; P. J. Silverman; E. J. Lloyd; Y. Kim; H. Luftman; M. Furtsch; T. Schiml; S. J. Hillenius

W-polycide dual-gate structure for sub- 1/4 micron low-voltage CMOS technology

J. Bevk, G. E. Georgiou, M. Frei, P. J. Silverman, E. J. Lloyd, Y. Kim, H. Luftman, M. Furtsch, T. Schiml, S. J. Hillenius

Research output: Contribution to journal › Conference article › peer-review

4 Scopus citations

Abstract

We describe a simple, low cost process, suitable for fabrication of low-voltage sub- 1/4 micron CMOS devices, utilizing W-polycide dual-gate structure. The novel feature of this process is a low gate stack profile (150-200nm), made possible by implanting dopants directly into tungsten silicide. The threshold voltage shifts due to lateral dopant diffusion between P- and NMOS devices with connected gates are minimized (<30mV) by combining thermal treatments with selective nitrogen gate co-implant to control dopant activation and diffusion. Both P-and NMOS devices have excellent I_on/I_off characteristics, low leakage currents, good short channel behavior and low gate sheet resistance of 8-10Ω/□.

Original language	English (US)
Pages (from-to)	893-896
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
State	Published - 1995
Externally published	Yes
Event	Proceedings of the 1995 International Electron Devices Meeting, IEDM'95 - Washington, DC, USA Duration: Dec 10 1995 → Dec 13 1995

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

@article{57b49c52d9114389b16263145732a25d,

title = "W-polycide dual-gate structure for sub- 1/4 micron low-voltage CMOS technology",

abstract = "We describe a simple, low cost process, suitable for fabrication of low-voltage sub- 1/4 micron CMOS devices, utilizing W-polycide dual-gate structure. The novel feature of this process is a low gate stack profile (150-200nm), made possible by implanting dopants directly into tungsten silicide. The threshold voltage shifts due to lateral dopant diffusion between P- and NMOS devices with connected gates are minimized (<30mV) by combining thermal treatments with selective nitrogen gate co-implant to control dopant activation and diffusion. Both P-and NMOS devices have excellent Ion/Ioff characteristics, low leakage currents, good short channel behavior and low gate sheet resistance of 8-10Ω/□.",

author = "J. Bevk and Georgiou, {G. E.} and M. Frei and Silverman, {P. J.} and Lloyd, {E. J.} and Y. Kim and H. Luftman and M. Furtsch and T. Schiml and Hillenius, {S. J.}",

year = "1995",

language = "English (US)",

pages = "893--896",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1995 International Electron Devices Meeting, IEDM'95 ; Conference date: 10-12-1995 Through 13-12-1995",

}

TY - JOUR

T1 - W-polycide dual-gate structure for sub- 1/4 micron low-voltage CMOS technology

AU - Bevk, J.

AU - Georgiou, G. E.

AU - Frei, M.

AU - Silverman, P. J.

AU - Lloyd, E. J.

AU - Kim, Y.

AU - Luftman, H.

AU - Furtsch, M.

AU - Schiml, T.

AU - Hillenius, S. J.

PY - 1995

Y1 - 1995

N2 - We describe a simple, low cost process, suitable for fabrication of low-voltage sub- 1/4 micron CMOS devices, utilizing W-polycide dual-gate structure. The novel feature of this process is a low gate stack profile (150-200nm), made possible by implanting dopants directly into tungsten silicide. The threshold voltage shifts due to lateral dopant diffusion between P- and NMOS devices with connected gates are minimized (<30mV) by combining thermal treatments with selective nitrogen gate co-implant to control dopant activation and diffusion. Both P-and NMOS devices have excellent Ion/Ioff characteristics, low leakage currents, good short channel behavior and low gate sheet resistance of 8-10Ω/□.

AB - We describe a simple, low cost process, suitable for fabrication of low-voltage sub- 1/4 micron CMOS devices, utilizing W-polycide dual-gate structure. The novel feature of this process is a low gate stack profile (150-200nm), made possible by implanting dopants directly into tungsten silicide. The threshold voltage shifts due to lateral dopant diffusion between P- and NMOS devices with connected gates are minimized (<30mV) by combining thermal treatments with selective nitrogen gate co-implant to control dopant activation and diffusion. Both P-and NMOS devices have excellent Ion/Ioff characteristics, low leakage currents, good short channel behavior and low gate sheet resistance of 8-10Ω/□.

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UR - http://www.scopus.com/inward/citedby.url?scp=18244424120&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:18244424120

SN - 0163-1918

SP - 893

EP - 896

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - Proceedings of the 1995 International Electron Devices Meeting, IEDM'95

Y2 - 10 December 1995 through 13 December 1995

ER -

W-polycide dual-gate structure for sub- 1/4 micron low-voltage CMOS technology

Abstract

All Science Journal Classification (ASJC) codes

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