W-polycide dual-gate structure for sub- 1/4 micron low-voltage CMOS technology

J. Bevk, G. E. Georgiou, M. Frei, P. J. Silverman, E. J. Lloyd, Y. Kim, H. Luftman, M. Furtsch, T. Schiml, S. J. Hillenius

Research output: Contribution to journalConference articlepeer-review

4 Scopus citations

Abstract

We describe a simple, low cost process, suitable for fabrication of low-voltage sub- 1/4 micron CMOS devices, utilizing W-polycide dual-gate structure. The novel feature of this process is a low gate stack profile (150-200nm), made possible by implanting dopants directly into tungsten silicide. The threshold voltage shifts due to lateral dopant diffusion between P- and NMOS devices with connected gates are minimized (<30mV) by combining thermal treatments with selective nitrogen gate co-implant to control dopant activation and diffusion. Both P-and NMOS devices have excellent Ion/Ioff characteristics, low leakage currents, good short channel behavior and low gate sheet resistance of 8-10Ω/□.

Original languageEnglish (US)
Pages (from-to)893-896
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - Dec 1 1995
Externally publishedYes
EventProceedings of the 1995 International Electron Devices Meeting, IEDM'95 - Washington, DC, USA
Duration: Dec 10 1995Dec 13 1995

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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