TY - JOUR
T1 - Write reconstruction for write throughput improvement on MLC PCM based main memory
AU - Luo, Huizhang
AU - Dai, Penglin
AU - Shi, Liang
AU - Xue, Chun Jason
AU - Zhuge, Qingfeng
AU - Sha, Edwin H.M.
N1 - Funding Information:
This work is supported by the Fundamental Research Funds for the Central Universities (106112016CDJZR185512 and 106112014CDJZR185502), NSFC ( 61402059 , 61472052 and 61572411 ), and National 863 Programs 2015AA015304.
PY - 2016/11/1
Y1 - 2016/11/1
N2 - The emerging Phase Change Memory (PCM) is considered as one of the most promising candidates to replace DRAM as main memory due to its better scalability and non-volatility. With multi-bit storage capability, Multiple-Level-Cell (MLC) PCM outperforms Single-Level-Cell (SLC) in density. However, the high write latency has been a performance bottleneck for MLC PCM for two reasons: First, MLC PCM has a much longer programming time; Second, the write latencies of different cell state transitions range significantly. When cells are concurrently written in the burst mode, the write latency of a burst is delayed by the worst state transitions. To improve the write throughput of MLC PCM based main memory, this paper proposes a Write Reconstruction (WR) scheme. WR reconstructs multiple burst writes targeting the same memory row, where the worst case cells are grouped together at some writes. With this approach, the write latency of other writes will be reduced. WR incurs low implementation overhead and shows significant efficiency. Experimental results show that WR achieves 18.1% of write latency reduction on average, with negligible power overhead.
AB - The emerging Phase Change Memory (PCM) is considered as one of the most promising candidates to replace DRAM as main memory due to its better scalability and non-volatility. With multi-bit storage capability, Multiple-Level-Cell (MLC) PCM outperforms Single-Level-Cell (SLC) in density. However, the high write latency has been a performance bottleneck for MLC PCM for two reasons: First, MLC PCM has a much longer programming time; Second, the write latencies of different cell state transitions range significantly. When cells are concurrently written in the burst mode, the write latency of a burst is delayed by the worst state transitions. To improve the write throughput of MLC PCM based main memory, this paper proposes a Write Reconstruction (WR) scheme. WR reconstructs multiple burst writes targeting the same memory row, where the worst case cells are grouped together at some writes. With this approach, the write latency of other writes will be reduced. WR incurs low implementation overhead and shows significant efficiency. Experimental results show that WR achieves 18.1% of write latency reduction on average, with negligible power overhead.
KW - Phase change memory (PCM)
KW - Write reconstruction
KW - Write throughput
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U2 - 10.1016/j.sysarc.2016.05.006
DO - 10.1016/j.sysarc.2016.05.006
M3 - Article
AN - SCOPUS:84977481071
SN - 1383-7621
VL - 71
SP - 62
EP - 72
JO - Journal of Systems Architecture
JF - Journal of Systems Architecture
ER -