Write strategies for 2 and 4-bit multi-level phase-change memory

T. Nirschl; J. B. Philipp; T. D. Happ; G. W. Burr; B. Rajendran; M. H. Lee; A. Schrott; M. Yang; M. Breitwisch; C. F. Chen; E. Joseph; M. Lamorey; R. Cheek; S. H. Chen; S. Zaidi; S. Raoux; Y. C. Chen; Y. Zhu; R. Bergmann; H. L. Lung; C. Lam

doi:10.1109/IEDM.2007.4418973

Write strategies for 2 and 4-bit multi-level phase-change memory

T. Nirschl, J. B. Philipp, T. D. Happ, G. W. Burr, B. Rajendran, M. H. Lee, A. Schrott, M. Yang, M. Breitwisch, C. F. Chen, E. Joseph, M. Lamorey, R. Cheek, S. H. Chen, S. Zaidi, S. Raoux, Y. C. Chen, Y. Zhu, R. Bergmann, H. L. LungC. Lam

Research output: Contribution to journal › Conference article › peer-review

238 Scopus citations

Abstract

We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4bits/cell and a 32kb memory page at 2bits/cell are experimentally demonstrated.

Original language	English (US)
Article number	4418973
Pages (from-to)	461-464
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting, IEDM
DOIs	https://doi.org/10.1109/IEDM.2007.4418973
State	Published - 2007
Externally published	Yes
Event	2007 IEEE International Electron Devices Meeting, IEDM - Washington, DC, United States Duration: Dec 10 2007 → Dec 12 2007

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1109/IEDM.2007.4418973

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Nirschl, T., Philipp, J. B., Happ, T. D., Burr, G. W., Rajendran, B., Lee, M. H., Schrott, A., Yang, M., Breitwisch, M., Chen, C. F., Joseph, E., Lamorey, M., Cheek, R., Chen, S. H., Zaidi, S., Raoux, S., Chen, Y. C., Zhu, Y., Bergmann, R., ... Lam, C. (2007). Write strategies for 2 and 4-bit multi-level phase-change memory. Technical Digest - International Electron Devices Meeting, IEDM, 461-464. Article 4418973. https://doi.org/10.1109/IEDM.2007.4418973

@article{2516c7f5212344179a6b6c7b45f4adc4,

title = "Write strategies for 2 and 4-bit multi-level phase-change memory",

abstract = "We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4bits/cell and a 32kb memory page at 2bits/cell are experimentally demonstrated.",

author = "T. Nirschl and Philipp, {J. B.} and Happ, {T. D.} and Burr, {G. W.} and B. Rajendran and Lee, {M. H.} and A. Schrott and M. Yang and M. Breitwisch and Chen, {C. F.} and E. Joseph and M. Lamorey and R. Cheek and Chen, {S. H.} and S. Zaidi and S. Raoux and Chen, {Y. C.} and Y. Zhu and R. Bergmann and Lung, {H. L.} and C. Lam",

year = "2007",

doi = "10.1109/IEDM.2007.4418973",

language = "English (US)",

pages = "461--464",

journal = "Technical Digest - International Electron Devices Meeting, IEDM",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2007 IEEE International Electron Devices Meeting, IEDM ; Conference date: 10-12-2007 Through 12-12-2007",

}

Nirschl, T, Philipp, JB, Happ, TD, Burr, GW, Rajendran, B, Lee, MH, Schrott, A, Yang, M, Breitwisch, M, Chen, CF, Joseph, E, Lamorey, M, Cheek, R, Chen, SH, Zaidi, S, Raoux, S, Chen, YC, Zhu, Y, Bergmann, R, Lung, HL & Lam, C 2007, 'Write strategies for 2 and 4-bit multi-level phase-change memory', Technical Digest - International Electron Devices Meeting, IEDM, pp. 461-464. https://doi.org/10.1109/IEDM.2007.4418973

TY - JOUR

T1 - Write strategies for 2 and 4-bit multi-level phase-change memory

AU - Nirschl, T.

AU - Philipp, J. B.

AU - Happ, T. D.

AU - Burr, G. W.

AU - Rajendran, B.

AU - Lee, M. H.

AU - Schrott, A.

AU - Yang, M.

AU - Breitwisch, M.

AU - Chen, C. F.

AU - Joseph, E.

AU - Lamorey, M.

AU - Cheek, R.

AU - Chen, S. H.

AU - Zaidi, S.

AU - Raoux, S.

AU - Chen, Y. C.

AU - Zhu, Y.

AU - Bergmann, R.

AU - Lung, H. L.

AU - Lam, C.

PY - 2007

Y1 - 2007

N2 - We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4bits/cell and a 32kb memory page at 2bits/cell are experimentally demonstrated.

AB - We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4bits/cell and a 32kb memory page at 2bits/cell are experimentally demonstrated.

UR - http://www.scopus.com/inward/record.url?scp=42149105894&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=42149105894&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2007.4418973

DO - 10.1109/IEDM.2007.4418973

M3 - Conference article

AN - SCOPUS:42149105894

SN - 0163-1918

SP - 461

EP - 464

JO - Technical Digest - International Electron Devices Meeting, IEDM

JF - Technical Digest - International Electron Devices Meeting, IEDM

M1 - 4418973

T2 - 2007 IEEE International Electron Devices Meeting, IEDM

Y2 - 10 December 2007 through 12 December 2007

ER -

Write strategies for 2 and 4-bit multi-level phase-change memory

Abstract

All Science Journal Classification (ASJC) codes

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