Write strategies for 2 and 4-bit multi-level phase-change memory

T. Nirschl, J. B. Philipp, T. D. Happ, G. W. Burr, B. Rajendran, M. H. Lee, A. Schrott, M. Yang, M. Breitwisch, C. F. Chen, E. Joseph, M. Lamorey, R. Cheek, S. H. Chen, S. Zaidi, S. Raoux, Y. C. Chen, Y. Zhu, R. Bergmann, H. L. LungC. Lam

Research output: Contribution to journalConference articlepeer-review

238 Scopus citations


We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4bits/cell and a 32kb memory page at 2bits/cell are experimentally demonstrated.

Original languageEnglish (US)
Article number4418973
Pages (from-to)461-464
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting, IEDM
StatePublished - 2007
Externally publishedYes
Event2007 IEEE International Electron Devices Meeting, IEDM - Washington, DC, United States
Duration: Dec 10 2007Dec 12 2007

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry


Dive into the research topics of 'Write strategies for 2 and 4-bit multi-level phase-change memory'. Together they form a unique fingerprint.

Cite this